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Memory protection
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#	Item
111	Clean Water Task Force - Group Memory #4 Add to Reading List Source URL: lincoln.ne.gov Language: English - Date: 2012-05-09 16:18:03 Water Environmental soil science Pollution Stormwater X Window System Surface runoff United States Environmental Protection Agency Water quality Water pollution Environment Earth
112	CHERI: A RISC capability machine for practical memory safety Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2014-07-08 10:34:26 Instruction set architectures Software engineering MIPS architecture Pointer Memory protection 64-bit Ring Capability-based addressing C Computer architecture Computing Memory management
113	RESEARCH “Novel vaccination strategies for induction of long-term immune memory and protection to bovine viral diarrhea virus” IMPROVED BVD VACCINE PROJECT NO.: [removed] Add to Reading List Source URL: albertabeef.org Language: English - Date: 2014-04-21 12:23:03 Health Virology Animal virology Viral diseases Bovine virus diarrhea Diarrhea DNA vaccination Vaccine Attenuated vaccine Vaccination Biology Medicine
114	How to Impress Girls with Browser Memory Protection Bypasses Add to Reading List Source URL: www.azimuthsecurity.com Language: English - Date: 2010-04-10 04:10:51 Address space layout randomization Alexander Sotirov Copyright law of the United States Internet Explorer 8 IBM Copyright Memory protection HTTP cookie Computing Software Data
115	Capability Hardware Enhanced RISC Instructions: CHERI Instruction-set architecture Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2014-06-18 09:34:49 Ring MIPS architecture Instruction set 64-bit Hypervisor Reduced instruction set computing Kernel Capability-based security Memory protection Computer architecture Central processing unit Instruction set architectures
116	Capability Hardware Enhanced RISC Instructions: CHERI Instruction-set architecture Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2014-07-14 10:03:30 MIPS architecture Ring Instruction set 64-bit Hypervisor Reduced instruction set computing Capability-based security Kernel Memory protection Computer architecture Central processing unit Instruction set architectures
117	BORN WITH A GREY BEARD: CANADAʼS NAVIGABLE WATERS PROTECTION ACT BY: KRYSTYN TULLY, LAKE ONTARIO WATERKEEPER Presented at the 6th Canadian River Heritage Conference Ottawa, Ontario June 15, 2009 Add to Reading List Source URL: www.chrs.ca Language: English - Date: 2011-06-30 16:42:59 Memory of the World Register Navigability Political history Legal history Cotton Library Magna Carta Manuscripts
118	Vx32: Lightweight User-level Sandboxing on the x86 Bryan Ford and Russ Cox Massachusetts Institute of Technology {baford,rsc}@pdos.csail.mit.edu Abstract Add to Reading List Source URL: pdos.csail.mit.edu Language: English - Date: 2014-09-23 03:33:32 X86 architecture Vx32 Virtual machines X86 assembly language X86 Memory protection 64-bit MOV Virtual memory Computer architecture System software Computing
119	nShield Security Policy ™ CI PHE R Add to Reading List Source URL: csrc.nist.gov Language: English - Date: 2010-01-28 00:00:00 Computer security FIPS 140-2 FIPS 140 PCI Express Security token Hardware security module Linux kernel Memory protection Access control Cryptography standards Computing Security
120	nShield Security Policy ™ CI PHE R Add to Reading List Source URL: csrc.nist.gov Language: English - Date: 2010-01-28 00:00:00 Computer security FIPS 140-2 FIPS 140 PCI Express Security token Hardware security module Linux kernel Memory protection Kernel Cryptography standards Computing Security

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